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10. Structural Modeling

Structural modeling was described briefly in the section Structural Modeling in “Basic Structure of a VHDL file”. A structural way of modeling describes a circuit in terms of components and its interconnection. Each component is supposed to be defined earlier (e.g. in package) and can be described as structural, a behavioral or dataflow model. At the lowest hierarchy each component is described as a behavioral model, using the basic logic operators defined in VHDL. In general structural modeling is very good to describe complex digital systems, though a set of components in a hierarchical fashion.


A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnections. VHDL provides a formal way to do this by


  • Declare a list of components being used
  • Declare signals which define the nets that interconnect components
  • Label multiple instances of the same component so that each instance is uniquely defined.


The components and signals are declared within the architecture body,


architecture architecture_name of NAME_OF_ENTITY is

     — Declarations

component declarations

           signal declarations


— Statements

           component instantiation and connections   


end architecture_name;


  1. Component declaration


Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface (ports). The syntax is as follows:


component component_name [is]

[port (port_signal_names: mode type;

           port_signal_names: mode type;


port_signal_names: mode type);]

end component [component_name];


The component name refers to either the name of an entity defined in a library or an entity explicitly defined in the VHDL file (see example of the four bit adder).


The list of interface ports gives the name, mode and type of each port, similarly as is done in the entity declaration.


A few examples of component declaration follow:


component OR2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;


component PROC

port (CLK, RST, RW, STP: in std_logic;

ADDRBUS: out std_logic_vector (31 downto 0);

DATA: inout integer range 0 to 1024);


component FULLADDER

port(a, b, c: in std_logic;

sum, carry: out std_logic);

end component;


As mentioned earlier, the component declaration has to be done either in the architecture body or in the package declaration. If the component is declared in a package, one does not have to declare it again in the architecture body as long as one uses the library and use clause.


  1. Component Instantiation and interconnections


The component instantiation statement references a component that can be


  • Previously defined at the current level of the hierarchy or
  • Defined in a technology library (vendor’s library).


The syntax for the components instantiation is as follows,


instance_name : component name

     port map (port1=>signal1, port2=> signal2,… port3=>signaln);


The instance name or label can be any legal identifier and is the name of this particular instance. The component name is the name of the component declared earlier using the component declaration statement. The port name is the name of the port and signal is the name of the signal to which the specific port is connected. The above port map associates the ports to the signals through named association. An alternative method is the positional association shown below,


     port map (signal1, signal2,…signaln);


in which the first port in the component declaration corresponds to the first signal, the second port to the second signal, etc. The signal position must be in the same order as the declared component’s ports. One can mix named and positional associations as long as one puts all positional associations before the named ones. The following examples illustrates this,


component NAND2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;

signal int1, int2, int3: std_logic;

architecture struct of EXAMPLE is

U1: NAND2 port map (A,B,int1);

U2: NAND2 port map (in2=>C, in2=>D, out1=>int2);

U3: NAND3 port map (in1=>int1, int2, Z);


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